1. Field of the Invention
The present invention relates to reliability and acceptance test devices for metal-oxide-semiconductor (MOS) fabrication, and more particularly, to an on-wafer AC stress test circuit.
2. Description of the Prior Art
As electronic devices become more a part of our everyday lives, demand for increased functionality, low power consumption, and smaller size has pushed discrete device fabrication technology into nanometer device sizes, with current processes supporting device sizes of 65 nm, and even 45 nm. Major advantages of smaller geometry device technologies include lower power consumption and ability to fit more dies on a wafer, or more devices on a die. At these dimensions, i.e. with gate lengths of 65 nm and 45 nm, oxide thicknesses decrease to 12 Angstroms (A) and lower.
One major disadvantage of smaller geometry device technologies is reduced life of the devices. Factors that reduce the life of the devices may differ for each progressively shrunken technology. In today's metal-oxide-semiconductor (MOS) technologies, at 65 nm and 45 nm, dielectric breakdown is a primary factor influencing device life. Thus, stress testing, which is a method used for extrapolating the device life by intentionally breaking down the dielectric with a high voltage input, becomes an important tool for determining reliability and yield. For 65 nm devices, which may operate at approximately 1.0V, the prior art relies on a direct current (DC) stress test to determine lifespan of the devices. Examples of typical DC stress tests include hot carrier injection (HCI) tests and Time Dependent Dielectric Breakdown (TDDB).
Please refer to FIG. 1, which is a diagram of a DC stress test setup according to the prior art. In FIG. 1, a typical MOS device 10 is fabricated in a substrate 100, and comprises a poly-silicon gate 110, a source doping region (source) 120, and a drain doping region (drain) 130. An oxide layer 140 is grown over a gap between the source 120 and the drain 130, and may slightly overlap the source 120 and the drain 130. In a 45 nm process, the oxide layer 140 has an oxide thickness under 12 A, and a high-k dielectric material is utilized to form the oxide layer 140, so as to reduce current leakage. To perform a TDDB test, a voltage source is coupled to a gate terminal Vg, and drain voltage or current is measured at a drain terminal Vd. The source 120 and the substrate 100 are both grounded. When the voltage source is applied to the gate terminal Vg, a channel 150 forms in the substrate 100 between the source 120 and the drain 130, which allows charged carriers, such as a charged carrier 151, to flow from the source 120 to the drain 130. However, the high-k dielectric material of the oxide layer 140 introduces phenomena such as Negative Bias Temperature Instability (NBTI), and charge trapping, which causes some charge carriers, such as a charge carrier 152, to be trapped in the oxide layer 140. As charge builds up in the oxide layer 140, a threshold voltage of the device 10 may be changed, degrading accuracy of the DC stress test result.
Charge trapping makes AC stress testing, or pulsed stress testing, ever more important. A typical solution for performing the AC stress test includes coupling an external pulse generator unit to a gate of a test device on a wafer, and measuring change in drain current of the test device. However, this requires external equipment over and above an external connection already utilized for the DC stress test, making the AC stress test hard to integrate with existing DC stress test designs.